1. Field of the Invention
This invention relates generally to data processing systems and more particularly to apparatus for enabling synchronization and information exchanges among independent asynchronous processors.
2. Description of the Prior Art
As the complexity of modern data processing units has increased, more control functions, formerly carried out by the central processing unit, have been delegated to other processing units. For example, it is now common for an input/output control subsystem to have its own control store for carrying out its required control functions. In like manner, it is now usual to connect to one another several central units and input/output control subsystems to constitute multiprocessor systems. In such multiprocessor systems, the several processes that the different processors carry out by themselves are not generally independent and it is therefore necessary for the different processors to communicate in order that the several processes go on in an orderly and synchronized way.
In the past communication apparatus among processors have been developed where the different synchronization information made use of both dedicated communication paths and dedicated resources (registers and read-write logic) in the several processors, without involving the working memory or memories of the system. This allows for the fast transfer of the required information, but it requires expensive and complex circuits and the use of conflict resolving logic when more than one processor is exchanging information at the same time or desires to use contemporaneously the same resource.
Alternately the working memory was used as an exchanging information buffer, thus realizing an independent communication network among processors only for the exchange of call and notification signals for calling a processor and notifying it of a memory address where the required information could be found. However this approach too has the disadvantage of requiring complex and expensive communication networks and additional mechanisms for conflict resolution. Conceptually the processor, to which the calling and notifying message is sent, is required to assume a subordinate or "slave" status as to the notifying processor ("master"). Besides it is necessary to arrange in the "slave" processor (and therefore in all the processors which can assume such status) resources able to receive the notifying "vector", that is, the whole notifying information as, for instance, the calling processor name and the memory address where the notifying information can be found. If such resources are not exclusively "dedicated" to this function, such resources can be busy in other tasks and the notification cannot be accepted. In this case the slave must signal with suitable messages if the notification has been accepted or not. Such an approach is, for instance, described in U.S. Pat. No. 4,000,485.